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mitsubishi lsis m5m5y5636tg ? 25,22,20 18874368-bit(524288-word by 36-bit) network sram 1 mitsubishi electric advanced information m5m5y5636tg rev.0.0 description the m5m5y5636tg is a family of 18m bit synchronous srams organized as 524288-words by 36-bit. it is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. mitsubishi's srams are fabricated with high performance, low power cmos technology, providing greater reliability. m5m5y5636tg operates on a single 1.8v power supply and are 1.8v cmos compatible. features ? fully registered inputs and outputs for pipelined operation ? fast clock speed: 250, 225, and 200 mhz ? fast access time: 2.6, 2.8, 3.2 ns ? single 1.8v +150/-100mv power supply v dd ? separate v ddq for 1.8v i/o ? individual byte write (bwa# - bwd#) controls may be tied low ? single read/write control pin (w#) ? echo clock outputs track data output drivers ? zq mode pin for user-selectable output drive strength ? 2 user programmable chip enable inputs for easy depth expansion ? linear or interleaved burst modes ? jtag boundary scan support application high-end networking products that require high bandwidth, such as switches and routers. function synchronous circuitry allows for precise cycle control triggered by a positive edge clock transition. synchronous signals include : all addresses, all data inputs, all chip enables (e1# , e2, e3), address advance/load (adv), byte write enables (bwa# , bwb#, bwc#, bwd #), echo clock outputs (cq1, cq1#, cq2, cq2#) and read/write (w#). write operations are controlled by the eight byte write enables (bwa# - bwd#) and read/write(w#) inputs. all writes are conducted with on-chip synchronous self-timed write circuitry. the echo clocks are delayed copies of the ram clock, clk. echo clocks are designed to track changes in output driver delays due to variance in die temperature and supply voltage. the zq pin supplied with selectable impedance drivers, allows selection between nominal drive strength (zq low) for multi- drop bus application and low drive strength (zq floating or high) point-to-point applications. the sense of two user-programmable chip enable inputs (e2, e3), whether they function as active low or active high inputs, is determined by the state of the programming inputs, ep2 and ep3. the linear burst order ( lbo#) is dc operated pin. lbo# pin will allow the choice of either an interleaved burst, or a linear burst. all read, write and deselect cycles are initiated by the adv low input. subsequent burst address can be internally generated as controlled by the adv high input. package part name table bump body size bump pitch m5m5y5636tg 209(11x19) bump bga 14mm x 22mm 1mm part name frequency access cycle active current (max.) standby current (max.) m5m5y5636tg -25 250mhz 2.6ns 4.0ns 400ma 20ma m5m5y5636tg -22 225mhz 2.8ns 4.4ns 380ma 20ma m5m5y5636tg -20 200mhz 3.2ns 5.0ns 360ma 20ma 2001.june rev.0.0 advanced information notice: this is not final specification. some parametric limits are subject to change.
mitsubishi lsis m5m5y5636tg ? 25,22,20 18874368-bit(524288-word by 36-bit) network sram 2 mitsubishi electric advanced information m5m5y5636tg rev.0.0 bump layout(top view) 209 bump bga 1 2 3 4 5 6 7 8 9 10 11 a nc nc a 6 e2 a 7 adv a 8 e3 a 9 dqb dqb b nc nc bwc# nc a 18 w# a 17 bwb# nc dqb dqb c nc nc nc bwd# nc e1# nc nc bwa# dqb dqb d nc nc v ss nc nc mcl nc nc v ss dqb dqb e nc dqpc v ddq v ddq v dd v dd v dd v ddq v ddq nc dqpb f dqc dqc v ss v ss v ss zq v ss v ss v ss nc nc g dqc dqc v ddq v ddq v dd ep2 v dd v ddq v ddq nc nc h dqc dqc v ss v ss v ss ep3 v ss v ss v ss nc nc j dqc dqc v ddq v ddq v dd mch v dd v ddq v ddq nc nc k cq2 cq2# clk nc v ss mcl v ss nc nc cq1# cq1 l nc nc v ddq v ddq v dd mch v dd v ddq v ddq dqa dqa m nc nc v ss v ss v ss mcl v ss v ss v ss dqa dqa n nc nc v ddq v ddq v dd mch v dd v ddq v ddq dqa dqa p nc nc v ss v ss v ss mcl v ss v ss v ss dqa dqa r dqpd nc v ddq v ddq v dd v dd v dd v ddq v ddq dqpa nc t dqd dqd v ss nc nc lbo# nc nc v ss nc nc u dqd dqd nc a 3 nc a 15 nc a 11 nc nc nc v dqd dqd a 5 a 4 a 16 a 1 a 13 a 12 a 10 nc nc w dqd dqd tms tdi a 2 a 0 a 14 tdo tck nc nc note1. mch means ? must connect high ? . mch should be connected to high. note2. mcl means ? must connect low ? . mcl should be connected to low.
mitsubishi lsis m5m5y5636tg ? 25,22,20 18874368-bit(524288-word by 36-bit) network sram 3 mitsubishi electric advanced information m5m5y5636tg rev.0.0 block diagram note3. the block diagram does not include the boundary scan logic. see boundary scan chapter. note4. the block diagram illustrates simplified device operation. see truth table, pin function and timing diagrams for detailed information. address register 19 write address register1 write address register2 a1 a0 linear/ interleaved burst counter d1 d0 q1 q0 a1' a0' 19 17 write registry and data coherency control logic byte a | byte d write drivers 256kx36 memory array output registers output select output buffers input register1 input register0 read logic 19 19 36 dqa lbo# dqpa dqb dqpb dqc dqpc dqd dqpd a0 a1 a2 ~ 18 clk e2 e1# e3 bwa# bwb# adv w# v dd v ddq v ss ep2 ep3 cq1 cq1# cq2 cq2# echo clock output buffers bwc# bwd# chip enable control logic zq echo clock output registers
mitsubishi lsis m5m5y5636tg ? 25,22,20 18874368-bit(524288-word by 36-bit) network sram 4 mitsubishi electric advanced information m5m5y5636tg rev.0.0 pin function pin name function a0 ~ a18 synchronous address inputs these inputs are registered and must meet the setup and hold times around the rising edge of clk. a0 and a1 are the two least significant bits (lsb) of the address field and set the internal burst counter if burst is desired. bwa#, bwb#, bwc#, bwd# synchronous byte write enables these active low inputs allow individual bytes to be written when a write cycle is active and must meet the setup and hold times around the rising edge of clk. byte writes need to be asserted on the same cycle as the address. bwa are associated with addresses and apply to subsequent data. bwa# controls dqa, dqpa pins; bwb# controls dqb, dqpb pins; bwc# controls dqc, dqpc pins; bwd# controls dqd, dqpd pins. clk clock input this signal registers the address, data, chip enables, byte write enables and burst control inputs on its rising edge. all synchronous inputs must meet setup and hold times around the clock's rising edge. e1# synchronous chip enable this active low input is used to enable the device and is sampled only when a new external address is loaded (adv is low). e2, e3 synchronous chip enable these pins are user-programmable chip enable inputs. the sense of the inputs, whether they function as active low or high inputs, is determined by the state of the programming inputs, ep2 and ep3. ep2, ep3 chip enable program pin these pins determine the sense of the user-programmable chip enable inputs, whether they function as active low or active high inputs. adv synchronous address advance/load when high, this input is used to advance the internal burst counter, controlling burst access after the external address is loaded. when high, w# is ignored. a low on this pin permits a new address to be loaded at clk rising edge. cq1, cq1#, cq2, cq2# echo clock outputs the echo clocks are delayed copies of the main ram clock, clk. zq output impedance control this pin allows selection between ram nominal drive strength (zq low) for multi-drop bus applications and low drive strength (zq floating or high) point-to-point application. w# synchronous read/write this active input determines the cycle type when adv is low. this is the only means for determining reads and writes. read cycles may not be converted into writes (and vice versa) other than by loading a new address. a low on the pin permits byte write operations and must meet the setup and hold times around the rising edge of clk. full bus width writes occur if all byte write enables are low. dqa,dqpa,dqb,dqpb, dqc,dqpc,dqd,dqpd synchronous data i/o byte ? a ? is dqa , dqpa pins; byte ? b ? is dqb, dqpb pins; byte ? c ? is dqc, dqpc pins; byte ? d ? is dqd,dqpd pins. input data must meet setup and hold times around clk rising edge. lbo# burst mode control this dc operated pin allows the choice of either an interleaved burst or a linear burst. if this pin is high or nc, an interleaved burst occurs. when this pin is low, a linear burst occurs, and input leak current to this pin. v dd v dd core power supply v ss v ss ground v ddq v ddq i/o buffer power supply tdi test data input tdo test data output tck test clock tms test mode select these pins are used for boundary scan test. mch must connect high these pins should be connected to high mcl must connect low these pins should be connected to low nc no connect these pins are not internally connected and may be connected to ground.
mitsubishi lsis m5m5y5636tg ? 25,22,20 18874368-bit(524288-word by 36-bit) network sram 5 mitsubishi electric advanced information m5m5y5636tg rev.0.0 read operation pipelined read read operation is initiated when the following conditions are satisfied at the rising edge of clock: all three chip enables (e1#, e2 and e3) are active, the write enable input signal (w#) is deasserted high, and adv is asserted low. the address presented to the address inputs is latched into the address register and presented to the memory core and control logic. the control logic determines that a read access is in progress and allows the requested data to propagate to the input of the output register. at the next rising edge of clock the read data is allowed to propagate through the output register and onto the output pins. clk a b c d e add e1# adv w# bwx# dq cq q(a) q(b) q(c) read a deselect read b read c read d read e
mitsubishi lsis m5m5y5636tg ? 25,22,20 18874368-bit(524288-word by 36-bit) network sram 6 mitsubishi electric advanced information m5m5y5636tg rev.0.0 write operation double late write write operation occurs when the following conditions are satisfied at the rising edge of clock: all three chip enables (e1#, e2 and e3) are active and the write enable input signal (w#) is asserted low. double late write means that data in is required on the third rising edge of clock. it is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. clk a c d e f add e1# adv w# bwx# dq cq q(a) q(c) b d(b) d(d) read a write b read c write d read e read f
mitsubishi lsis m5m5y5636tg ? 25,22,20 18874368-bit(524288-word by 36-bit) network sram 7 mitsubishi electric advanced information m5m5y5636tg rev.0.0 special function burst cycles the sram provides an on-chip burst address generator that can be utilized, if desired, to further simplify burst read or write implementations. the adv control pin, when driven high, commands the sram to advance the internal address counter and use the counter generated address to read or write the sram. the starting address for the first cycle in a burst cycle series is loaded into the sram by driving the adv pin low, into load mode. clk add e1# adv w# bwx# dq cq d(a+3) write a burst write a+1 a d(a+2) d(a+1) d(a) burst write a+2 burst write a+3 burst write a b write b clk a add e1# adv w# bwx# dq cq q(a) q(a+1) q(a+2) q(a+3) read a burst read a+1 burst read a+2 burst read a+3 read b b burst read b+1 burst read burst write
mitsubishi lsis m5m5y5636tg ? 25,22,20 18874368-bit(524288-word by 36-bit) network sram 8 mitsubishi electric advanced information m5m5y5636tg rev.0.0 dc operated truth table name input status operation high or nc interleaved burst sequence lbo# low linear burst sequence note5. lbo# is dc operated pin. note6. nc means no connection. note7. see burst sequence table about interleaved and linear burst sequence. burst sequence table (1) interleaved burst sequence (when lbo# = high or nc) operation a18 ~ a2 a1,a0 first access, latch external address a18 ~ a2 0 , 0 0 , 1 1 , 0 1 , 1 second access(first burst address) latched a18 ~ a2 0 , 1 0 , 0 1 , 1 1 , 0 third access(second burst address) latched a18 ~ a2 1 , 0 1 , 1 0 , 0 0 , 1 fourth access(third burst address) latched a18 ~ a2 1 , 1 1 , 0 0 , 1 0 , 0 (2) linear burst sequence (when lbo# = low) operation a18 ~ a2 a1,a0 first access, latch external address a18 ~ a2 0 , 0 0 , 1 1 , 0 1 , 1 second access(first burst address) latched a18 ~ a2 0 , 1 1 , 0 1 , 1 0 , 0 third access(second burst address) latched a18 ~ a2 1 , 0 1 , 1 0 , 0 0 , 1 fourth access(third burst address) latched a18 ~ a2 1 , 1 0 , 0 0 , 1 1 , 0 note8. the burst sequence wraps around to its initial state upon completion.
mitsubishi lsis m5m5y5636tg ? 25,22,20 18874368-bit(524288-word by 36-bit) network sram 9 mitsubishi electric advanced information m5m5y5636tg rev.0.0 echo clock the sram feature s echo clocks, cq1,cq2, cq1 # , and cq2 # that track the performance of the output drivers. the echo clocks are delayed copies of the main ram clock, c l k. echo clocks are designed to track changes in output driver delays due to variance in die temperature and supply voltage. the echo clocks are designed to fire with the rest of the data output drivers. the sram provide both in-phase, or true, echo clock outputs (cq1 and cq2) and inverted echo clock outputs (cq1 # and cq2 # ). it should be noted that deselection of the s ram via e2 and e3 also deselects the echo clock output drivers. the deselection of echo clock drivers is always pipelined to the same degree as output data. deselection of the s ram via e1 # does not deactivate the echo clocks. programmable enable the sram features two user programmable chip enable inputs, e2 and e3. the sense of the inputs, whether they function as active low or active high inputs, is determined by the state of the programming inputs, ep2 and ep3. for example, if ep2 is held at high, e2 functions as an active high enable. if ep2 is held to low, e2 functions as an active low chip enable input. programmability of e2 and e3 allows for banks of depth expansion to be accomplished with no additional logic. by programming the enable inputs of four srams in binary sequence (00,01,10,11) and driving the enable inputs with two address inputs, four srams can be made to look like one larger sram to the system. bank enable truth table ep2 ep3 e2 e3 bank0 low low active low active low bank1 low high active low active high bank2 high low active high active low bank3 high high active high active high a e3# e2# e1# ck w# dq cq bank0 a 0 ~ a 20 7 e1# ck w# dqa ~ dqd a 0 ~ a 18 a 19 a 20 a e3 e2# e1# ck w# dq cq bank1 a 0 ~ a 18 a 19 a 20 a e3# e2 e1# ck w# dq cq bank2 a 0 ~ a 18 a 19 a 20 a e3 e2 e1# ck w# dq cq bank3 a 0 ~ a 18 a 19 a 20 cq example four bank depth schematic
mitsubishi lsis m5m5y5636tg ? 25,22,20 18874368-bit(524288-word by 36-bit) network sram 10 mitsubishi electric advanced information m5m5y5636tg rev.0.0 it should be noted that deselection of the s ram via e2 and e3 also deselects the echo clock output drivers. the deselection of echo clock drivers is always pipelined to the same degree as output data. deselection of the s ram via e1 # does not deactivate the echo clocks. clk a add e1# e2# bank1 q(a) q(c) e2 bank2 b c d e f dq bank1 cq bank1 cq bank1 + cq bank2 q(b) q(d) dq bank2 cq bank2 echo clock control in two banks note9. e1 # does not deselect the echo clock outputs. echo clock outputs are synchronously deselected by e2 or e3 being sampled false.
mitsubishi lsis m5m5y5636tg ? 25,22,20 18874368-bit(524288-word by 36-bit) network sram 11 mitsubishi electric advanced information m5m5y5636tg rev.0.0 in some applications it may be appropriate to pause between banks; to deselect both s rams with e1 # before resuming read operations. an e1 # deselect at a bank switch will allow at least one clock to be issued from the new bank before the first read cycle in the bank. although the following drawing illustrates a e1 # read pause upon switching from bank 1 to bank 2, a write to bank 2 would have the same effect, causing the s ram in bank 2 to issue at least one clock before it is needed. output driver impedance control the zq pin of s rams supplied with selectable impedance drivers, allows selection between sram nominal drive strength (zq low) for multi-drop bus applications and low drive strength (zq floating or high) point-to-point applications. clk a add e1# e2# bank1 q(a) e2 bank2 b c d e dq bank1 cq bank1 cq bank1 + cq bank2 q(b) q(c) dq bank2 cq bank2 pipelined read bank switch with e1# deselect note10. e1 # does not deselect the echo clock outputs. echo clock outputs are synchronously deselected by e2 or e3 being sampled false.
mitsubishi lsis m5m5y5636tg ? 25,22,20 18874368-bit(524288-word by 36-bit) network sram 12 mitsubishi electric advanced information m5m5y5636tg rev.0.0 truth table clk e1# (t n ) e (t n ) adv (t n ) w# (t n ) bw# (t n ) previous operation current operation dq/cq (t n ) dq/cq (t n+1 ) dq/cq (t n+2 ) l->h x f l x x x bank deselect *** high-z --- l->h x x h x x bank deselect bank deselect (continue) high-z high-z --- l->h h t l x x x deselect *** high-z / cq --- l->h x x h x x deselect deselect (continue) high-z / cq high-z / cq --- l->h l t l l t x write loads new address stores dqx if bwx#=low *** *** d n / cq (t n ) l->h l t l l f x write (abort) loads new address no data stored *** *** high-z / cq l->h x x h x t write write continue increments address by 1 stores dqx if bwx#=low *** d n-1 / cq (t n-1 ) d n / cq (t n ) l->h x x h x f write write continue (abort) increments address by 1 no data stored *** d n-1 / cq (t n-1 ) high-z / cq l->h l t l h x x read loads new address *** q n / cq (t n ) --- l->h x x h x x read read continue increments address by 1 q n-1 / cq (t n-1 ) q n / cq (t n ) --- note11. if e2=ep2 and e3=ep3 then e= ? t ? else e= ? f ? . note12. if one or more bwx#=low then bw#= ? t ? else bw#= ? f ? . note13. ? h ? = input ? high ? ; ? l ? = input ? low ? ; ? x ? = input ? don ? t care ? ; ? t ? = input ? true ? ; ? f ? = input ? false ? . note14. ? *** ? = indicates that the dq input requirement / output state and cq output state are determined by the previous operation. note15. ? --- ? = indicates that the dq input requirement / output state and cq output state are determined by the next operation. note16. dqs are tri-stated in response to bank deselect, deselect and write commands, one full cycle after the command is sampled. note17. cqs are tri-stated in response to bank deselect commands only, one full cycle after the command is sampled. note18. up to three (3) continue operations may be initiated after a read or write operation is initiated to burst transfer up to four (4) distinct pieces of data per single external address input. if a fourth (4) continue operation is initiated, the internal address wraps back to the initial external (base) address. write truth table w# bwa# bwb# bwc# bwd# function h x x x x read l l h h h write byte ? a ? l h l h h write byte ? b ? l h h l h write byte ? c ? l h h h l write byte ? d ? l l l l l write all bytes l h h h h write abort / nop note19. x means "don't care". h means logic high. l means logic low. note20. all inputs must meet setup and hold times around the rising edge (low to high) of clk.
mitsubishi lsis m5m5y5636tg ? 25,22,20 18874368-bit(524288-word by 36-bit) network sram 13 mitsubishi electric advanced information m5m5y5636tg rev.0.0 state diagram note21. the notation ? x, x, x, x ? controlling the state transitions above indicate the states of inputs e1#, e, adv, and w# respectively. note22. if (e2=ep2 and e3=ep3) then e= ? t ? else e= ? f ? . note23. ? h ? = input ? high ? ; ? l ? = input ? low ? ; ? x ? = input ? don ? t care ? ; ? t ? = input ? true ? ; ? f ? = input ? false ? . bank deselect deselect write read h, t, l, x or x, x, h, x l, t, l, l x, f, l, x write continue x, f, l, x l, t, l, l x, x, h, x x, x, h, x h, t, l, x h, t, l, x h, t, l, x x, f, l, x l, t, l, h l, t, l, l write continue x, f, l, x x, x, h, x h, t, l, x l, t, l, h x, x, h, x l, t, l, h l, t, l, l l, t, l, l l, t, l, h h, t, l, x x, f, l, x l, t, l, h l, t, l, l l, t, l, h x, f, l, x or x, x, h, x current state (n) next state (n+1) f transition input command code key f current state f f f next state n n+1 n+2 n+3 clock command current state & next state definition for read/write control state diagram
mitsubishi lsis m5m5y5636tg ? 25,22,20 18874368-bit(524288-word by 36-bit) network sram 14 mitsubishi electric advanced information m5m5y5636tg rev.0.0 absolute maximum ratings symbol parameter conditions ratings unit v dd power supply voltage -0.5* ~ 2.5 v v ddq i/o buffer power supply voltage -0.5* ~ 2.5 v v i input voltage -0.5 ~ v ddq +0.5( 2.5v max.) ** v v o output voltage with respect to v ss -0.5 ~ v ddq +0.5( 2.5v max.) ** v pd maximum power dissipation (v dd ) 780 mw t opr operating temperature 0 ~ 70 c t stg(bias) storage temperature(bias) -10 ~ 85 c t stg storage temperature -65 ~ 150 c note24. * this is - 1.0v ~ 3.6v when pulse width 2ns, and - 0.5v ~ 2.5v in case of dc. ** this is - 1.0v ~ v ddq +1.0v( 3.6v max.) when pulse width 2ns, and ? 0.5v ~ v ddq +0.5v in case of dc. dc electrical characteristics (1) power supplies limits symbol parameter condition min max unit v dd power supply voltage 1.70 1.95 v v ddq i/o buffer power supply voltage 1.70 1.95 v (2) cmos i/o dc input characteristics limits symbol parameter condition min max unit v ih high-level input voltage 0.65*v ddq v ddq +0.3 v v il low-level input voltage -0.3* 0.35*v ddq v note25. *v il min is ? 1.0v and v ih max is v ddq +1.0v(max. 3.6v) in case of ac (pulse width 2ns). (3) input and output leakage characteristics limits symbol parameter condition min max unit input leakage current (except ep2, ep3, lbo#, zq, mch, mcl pins) v i = 0v ~ v ddq 10 a i il input leakage current of ep2, ep3, lbo#, zq, mch, mcl pins v i = 0v ~ v ddq 10 a i ol output leakage current v i/o = 0v ~ v ddq 10 a
mitsubishi lsis m5m5y5636tg ? 25,22,20 18874368-bit(524288-word by 36-bit) network sram 15 mitsubishi electric advanced information m5m5y5636tg rev.0.0 (4) selectable impedance output driver dc electrical characteristics limits symbol parameter condition min max unit v ohl low drive output high voltage i ohl = -4ma v ddq -0.4v v v oll low drive output low voltage i oll = 4ma 0.4 v v ohh high drive output high voltage i ohh = -8ma v ddq -0.4v v v olh high drive output low voltage i olh = 8ma 0.4 v note26. zq=h; high impedance output driver setting note27. zq=l; low impedance output driver setting (5) operating currents limits symbol parameter condition min max unit 4.0ns cycle (250mhz) 400 4.4ns cycle (225mhz) 380 i cc1 power supply current : operating device selected; output open all other inputs v i v il or v i 3 v ih 5.0ns cycle (200mhz) 360 ma 4.0ns cycle (250mhz) 140 4.4ns cycle (225mhz) 110 i cc2 power supply current :chip disable and bank deselect e1# 3 v ih or (e2 or e3 false) output open all other inputs v i v il or v i 3 v ih 5.0ns cycle (200mhz) 100 ma i cc3 cmos standby current (clk stopped standby mode) device deselected; output open clk frequency=0hz all inputs v i v ss +0.1v or v i 3 v ddq -0.1v 20 ma capacitance limits symbol parameter condition min typ max unit c i input capacitance v i =gnd, v i =25mvrms, f=1mhz 6 pf c o input / output (dq) capacitance v o =gnd, v o =25mvrms, f=1mhz 8 pf note28. this parameter is sampled. thermal resistance limits symbol parameter condition min typ max unit q ja thermal resistance junction ambient tbd tbd pf q jc thermal resistance junction to case tbd tbd pf
mitsubishi lsis m5m5y5636tg ? 25,22,20 18874368-bit(524288-word by 36-bit) network sram 16 mitsubishi electric advanced information m5m5y5636tg rev.0.0 ac electrical characteristics (ta=0 ~ 70 c, v dd =1.70 ~ 1.95v, unless otherwise noted) (1) measurement condition input pulse levels v ih =v ddq , v il =0v input rise and fall times faster than or equal to 1v/ns input timing reference levels v ih =v il =v ddq / 2 output reference levels v ih =v il =v ddq / 2 output load fig.1 note29.valid delay measurement is made from the v ddq /2 on the input waveform to the v ddq /2 on the output waveform. input waveform should have a slew rate of faster than or equal to 1v/ns. note30.tri-state toff measurement is made from the v ddq /2 on the input waveform to the output waveform moving 20% from its initial to final value v ddq /2. note:the initial value is not v ol or v oh as specified in dc electrical characteristics table. note31. tri-state ton measurement is made from the v ddq /2 on the input waveform to the output waveform moving 20% from its initial value v ddq /2 to its final value. note:the final value is not v ol or v oh as specified in dc electrical characteristics table. note32.clocks,data,address and control signals will be tested with a minimum input slew rate of faster than or equal to 1v/ns. z o =50 w 50 w q v t =v ddq / 2 30pf (including wiring and jig) fig.1 output load v ddq / 2 v ddq / 2 t plh t phl input waveform output waveform v ddq / 2 input waveform vh-(0.2(vh-vz)) vz+(0.2(vh-vz)) 0.2(vz-vl) vz-(0.2(vz-vl)) toff ton vz (toff) (ton) vh vl output waveform fig.2 tdly measurement fig.3 tri-state measurement
mitsubishi lsis m5m5y5636tg ? 25,22,20 18874368-bit(524288-word by 36-bit) network sram 17 mitsubishi electric advanced information m5m5y5636tg rev.0.0 (2)timing characteristics limits 250mhz 225mhz 200mhz -25 -22 -20 symbol parameter min max min max min max unit clock t khkh clock cycle time 4.0 4.4 5.0 ns t khkl clock high time 1.5 1.6 1.8 ns t klkh clock low time 1.5 1.6 1.8 ns output times t khqv clock high to output valid 2.6 2.8 3.2 ns t khqx clock high to output invalid 0.5 0.6 0.7 ns t khqx1 clock high to output in low-z 0.5 0.6 0.7 ns t khqz clock high to output in high-z 0.5 2.6 0.6 2.8 0.7 3.2 ns t chcl echo clock high time 1.25 1.35 1.55 ns t clch echo clock low time 1.25 1.35 1.55 ns t khch clock high to echo clock high 0.5 2.5 0.5 2.7 0.5 3.1 ns t klcl clock low to echo clock low 0.5 2.5 0.5 2.7 0.5 3.1 ns t khcx1 clock high to echo clock low-z 0.5 0.5 0.5 ns t khcz clock high to echo clock high-z 0.5 2.5 0.5 2.7 0.5 3.1 ns t chqv echo clock high to output valid 0.5 0.5 0.5 ns t chqx output invalid to echo clock high -0.5 -0.5 -0.5 ns setup times t avkh address valid to clock high 0.8 1.0 1.2 ns t advvkh adv valid to clock high 0.8 1.0 1.2 ns t wvkh write valid to clock high 0.8 1.0 1.2 ns t bxvkh byte write valid to clock high (bwa# ~ bwd#) 0.8 1.0 1.2 ns t evkh enable valid to clock high (e1#,e2,e3) 0.8 1.0 1.2 ns t dvkh data in valid clock high 0.8 1.0 1.2 ns hold times t khax clock high to address don ? t care 0.5 0.5 0.5 ns t khadvx clock high to adv don ? t care 0.5 0.5 0.5 ns t khwx clock high to write don ? t care 0.5 0.5 0.5 ns t khbxx clock high to byte write don ? t care (bwa# ~ bwd#) 0.5 0.5 0.5 ns t khex clock high to enable don ? t care (e1#,e2,e3) 0.5 0.5 0.5 ns t khdx clock high to data in don ? t care 0.5 0.5 0.5 ns note33. test conditions is specified with the output loading shown in fig.1 unless otherwise noted. note34. t khqx1 , t khqz , t khcx1 , t khcz are sampled. note35. lbo#, ep2, ep3, zq is static and must not change during normal operation.
mitsubishi lsis m5m5y5636tg ? 25,22,20 18874368-bit(524288-word by 36-bit) network sram 18 mitsubishi electric advanced information m5m5y5636tg rev.0.0 timing parameter key t khqv t khqx1 t khcx1 t clch t chcl t khqz t khqx t khax t avkh t chqx t khkh t klkh t khkl clk add dq cq c d e qb t khax t avkh t khkh t klkh t khkl clk add dq a b c e1#, e2, e3 w#, bwx#, adv t nvkh t khnx qa t dvkh t khdx note36. t nvkh =t evkh , t wvkh , t bxvkh , t advvkh , etc. and t khnx =t khex , t khwx , t khbxx , t khadvx , etc. =cq high-z t chqv t khch t khcz t klcl
mitsubishi lsis m5m5y5636tg ? 25,22,20 18874368-bit(524288-word by 36-bit) network sram 19 mitsubishi electric advanced information m5m5y5636tg rev.0.0 jtag port operation overview the jtag port on this sram operates in a manner consistent with ieee standard 1149.1-1990, a serial boundary scan interface standard (commonly referred to as jtag), but dose not implement all of the function required for 1149.1 compliance. unlike jtag implementations that have been common among sram vendors for the last several years, this implementation dose offer a form of extest, known as clock assisted extest, reducing or eliminating the "hand coding" that has been required to overcome the test program compiler errors caused by previous non-compliant implementation. the jtag port interfaces with conventional cmos logic level signaling. disabling the jtag port it is possible to use this device without utilizing the jtag port. the port is reset at power-up and will remain inactive unless clocked. to assure normal operation of the sram with the jtag port unused, the tck, tdi and tms pins may be left floating or tied to high. the tdo pin should be left unconnected. jtag pin description test clock (tck) the tck input is clock for all tap events. all inputs are captured on the rising edge of tck and the test data out (tdo) propagates from the falling edge of tck. test mode select (tms) the tms input is sampled on the rising edge of tck. this is the command input for the tap controller state machine. an undriven tms input will produce the same result as a logic one input level. test data in (tdi) the tdi input is sampled on the rising edge of tck. this is the input side of the serial registers placed between the tdi and tdo pins. the register placed between the tdi and tdo pins is determined by the state of the tap controller state machine and the instruction that is currently loaded in the tap instruction resister (refer to the tap controller state diagram). an undriven tdi input will produce the same result as a logic one input level. test data out (tdo) the tdo output is active depending on the state of the tap controller state machine. output changes in response to the falling edge of tck. this is the output side of the serial registers placed between the tdi and tdo pins. note: this device dose not have a trst (tap reset) pin. trst is optional in ieee 1149.1. the test-logic-reset state is entered while tms is held high for five rising edges of tck. the tap controller is also reset automatically at power-up. jtag port registers overview the various jtag registers, referred to as test access port or tap registers, are selected (one at a time) via the sequence of 1s and 0s applied to tms as tck is strobed. each of tap registers are serial shift registers that capture serial input data on the rising edge of tck and push serial data out on the next falling edge of tck. when a register is selected, it is placed between the tdi and tdo pins. instruction register the instruction register holds the instructions that are executed by the tap controller when it is moved into the run-test/idle, or the
mitsubishi lsis m5m5y5636tg ? 25,22,20 18874368-bit(524288-word by 36-bit) network sram 20 mitsubishi electric advanced information m5m5y5636tg rev.0.0 various data register states. instructions are 3 bits long. the instruction resister can be loaded when it is placed between the tdi and tdo pins. the instruction resister is automatically preloaded with the idcode instruction at power-up or whenever the controller is placed in the test-logic-reset state. bypass register the bypass resister is a single-bit register that can be placed between the tdi and tdo pins. it allows serial test data to be passed through the sram's jtag port to another device in the scan chain with as little delay as possible. boundary scan register the boundary scan register is a collection of flip flops that can be preset by the logic level found on the sram's input or i/o pins. the flip flops are then daisy chained together so the levels found can be shifted serially out of the jtag port's tdo pins. the boundary scan register also includes a number of place holder flip flops (always set to a logic 1). the relationship between the device pins and the bits in the boundary scan register is described in the scan order table following. the boundary scan register, under the control of the tap controller, is loaded with the contents of the sram's i/o ring when the controller is in the capture-rd state and then is placed between the tdi and tdo pins when the controller is moved to the shift-dr state. sample-z, sample/preload and extest instruction can be used to activate the boundary scan register. identification (id) register the id register is a 32-bit register that is loaded with a device and vender specific 32-bit code when the controllers put in the capture-dr state with the idcode instruction loaded in the instruction register. the code is loaded from 32-bit on-chip rom. it describes various attributes of the sram (see page 25). the register is then placed between the tdi and tdo pins when the controller is moved into the shift-dr state. bit 0 in the register is the lsb and the first to reach the tdo pin when shifting begins. tap controller instruction set overview there are two classes of instructions defined in the standard 1149.1-1990; standard (public) instructions, and device specific (private) instructions. some public instructions are mandatory for 1149.1 compliance. optional public instructions must be implemented in prescribed ways. although the tap controller in this device follows the 1149.1 conventions, it is not 1194.1-compliant because one of the mandatory instructions, extest, is uniquely implemented. the tap on this device may be used to monitor all input and i/o pads. this device will not perform intest but can perform the preload portion of the sample/preload command. when the tap controller is placed in the capture-ir state, the two least significant bits of the instruction register are loaded with 01. when the tap controller is moved to the shift-ir state, the instruction register is placed between the tdi and tdo pins. in this state the desired instruction is serially loaded through the tdi input (while the previous contents are shifted out at the tdo output). for all instructions, the tap executes newly loaded instructions only when the controller is moved to the update-ir state. the tap instruction set for this device is listed in the following table. instruction descriptions bypass when the bypass instruction is loaded in the instruction register, the bypass register is placed between the tdi and tdo pins. this occurs when the tap controller is moved to the shift-dr state. this allows the board level scan path to be shortened to facilitate testing of other devices in the scan path. sample/preload sample/preload is a standard1149.1 mandatory public instruction. when the sample/preload instruction is loaded in the instruction register, moving the tap controller into the capture-dr state loads the data in the sram's input and i/o buffers into the boundary scan register. some boundary scan register locations are not associated with an input or i/o pin, and are loaded with the default state identified in the bsdl file. because the sram clock is independent from the tap clock (tck) it is possible for the tap to attempt to capture the i/o ring contents while the input buffers are in transition (i.e. in a metastable state). although allowing the tap to
mitsubishi lsis m5m5y5636tg ? 25,22,20 18874368-bit(524288-word by 36-bit) network sram 21 mitsubishi electric advanced information m5m5y5636tg rev.0.0 sample metastable inputs will not harm the device, repeatable results cannot be expected. sram input signals must be stabilized for long enough to meet the tap's input data capture set-up plus hold time (tts plus tth). the sram's clock inputs need not be paused for any other tap operation except capturing the i/o ring contents into the boundary scan register. moving the controller to the shift-dr state then places the boundary scan register between the tdi and tdo pins. extest-a extest is an ieee 1149.1 mandatory public instruction. it is to be executed whenever the instruction register is loaded with all logic 0s. the extest command dose not block or override the sram's input pins; therefore, the sram's internal state is still determined by its input pins. typically, the boundary scan register is loaded with the desired pattern with the sample/preload command. then the extest command is used to output the boundary scan register's contents, in parallel, on the sram's data output drivers on the falling edge of tck when the controller is in the update-ir state. alternately, the boundary scan register may loaded in parallel using the extest command. when the extest instruction is selected, the state of all sram's input and i/o pins, as well as the default values at scan register locations not associated with a pin, are transferred in parallel into the boundary scan register on the rising edge of tck in the capture-dr state, the sram's output pins drive out the value of the boundary scan register location with which each output pin is associated. the extest implementation in this device dose not, without further user intervention, actually move the contents of the scan chain onto the sram's output pins. therefore this device is not strictly 1149.1-compliant. to push data from the boundary scan registers, in parallel, out onto the sram's i/o and output pins, the sram's main clock (ck) must be pulsed. a single ck transition is sufficient to transfer the data, but more transitions will do no harm. idcode the idcode instruction cause the id rom to be loaded into the id register when the controller is in the capture-dr state and places the id register between the tdi and tdo pins in the shift-dr state. the idcode instruction is the default instruction loaded in at power-up and any time the controller is placed in the test-logic-reset state. sample-z if the sample-z instruction is loaded in the instruction register, all sram outputs are forced to an inactive drive state (high-z) and the boundary scan register is placed between the tdi and tdo pins when the tap controller is moved to the shift-dr state. rfu these instructions are reserved for future use. do not use these instructions.
mitsubishi lsis m5m5y5636tg ? 25,22,20 18874368-bit(524288-word by 36-bit) network sram 22 mitsubishi electric advanced information m5m5y5636tg rev.0.0 jtag tap block diagram boundary scan order tbd 31 30 29 . . . . . . 2 1 0 . . 2 1 0 0 . . . . . . . . . . . . . . . . 2 1 0 . . boundary scan register identification register instruction register bypass register tdo tdi test access port (tap) controller tms tck
mitsubishi lsis m5m5y5636tg ? 25,22,20 18874368-bit(524288-word by 36-bit) network sram 23 mitsubishi electric advanced information m5m5y5636tg rev.0.0 jtag tap controller state diagram tap controller dc electrical characteristics (ta=0 ~ 70 c, v dd =1.70 ~ 1.95v, unless otherwise noted) limits symbol parameter condition min max unit v iht test port input high voltage 0.65*v ddq v ddq +0.3 ** v v ilt test port input low voltage -0.3 ** 0.35*v ddq v v oht test port output high voltage i oh =-100 a v ddq -0.1 - v v olt test port output low voltage i ol =+100 a - 0.1 v i int tms, tck and tdi input leakage current -10 10 a i olt tdo output leakage current output disable, v out =0v ~ v ddq -10 10 a note37. **input undershoot/overshoot voltage must be ? 1.0v mitsubishi lsis m5m5y5636tg ? 25,22,20 18874368-bit(524288-word by 36-bit) network sram 24 mitsubishi electric advanced information m5m5y5636tg rev.0.0 tap controller ac electrical characteristics (ta=0 ~ 70 c, v dd =1.70 ~ 1.95v, unless otherwise noted) (1)measurement condition input pulse levels v ih =v ddq , v il =0v input rise and fall times faster than or equal to 1v/ns input timing reference levels v ih =v il =v ddq / 2 output reference levels v ih =v il =v ddq / 2 output load fig.4 (2)timing characteristics limits symbol parameter min max unit ttf tck frequency 20 mhz ttkc tck cycle time 50 ns ttkh tck high pulse width 20 ns ttkl tck low pulse width 20 ns tts tdi, tms setup time 10 ns tth tdi, tms hold time 10 ns ttkq tck low to tdo valid 20 ns (3) timing tck tdo tms tdi ttkc ttkh ttkl tts tth tts tth ttkq z o =50 w 50 w q v t =v ddq / 2 30pf (including wiring and jig) fig.4 output load
mitsubishi lsis m5m5y5636tg ? 25,22,20 18874368-bit(524288-word by 36-bit) network sram 25 mitsubishi electric advanced information m5m5y5636tg rev.0.0 jtag tap instruction set summary instruction code description extest-a 000 captures i/o ring contents. places the boundary scan register between tdi and tdo. this sram implements an clock assisted extest function. not 1149.1 compliant. idcode 001 preloads id register and places it between tdi and tdo sample-z 010 captures i/o ring contents. places the boundary scan register between tdi and tdo. forces all data and clock output drivers to high-z rfu 011 do not use this instruction; reserved for future use. sample/preload 100 captures i/o ring contents. places the boundary scan register between tdi and tdo. rfu 101 do not use this instruction; reserved for future use. rfu 110 do not use this instruction; reserved for future use. bypass 111 places the bypass register between tdi and tdo. structure of identification register device information revision v dd capacity function width gen. jedec vendor code of mitsubishi bit no. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 m5m5y5636 0 0 0 0 0 1 0 0 1 0 1 0 1 0 0 0 1 1 0 0 0 0 0 0 0 0 1 1 1 0 0 1 msb lsb note38. bit of device information ? gen.(generation) ? means bit no. 13 12 1 st generation 0 0 2 nd generation 0 1 3 rd generation 1 0 note39. bit of device information ? width ? means bit no. 16 15 14 x16 0 0 0 x18 0 0 1 x32 0 1 0 x36 0 1 1 x64 1 0 0 x72 1 0 1 note40. bit of device information ? function ? means bit no. 20 19 18 17 network sram 0 1 0 0 pb 0 0 0 1 note41. bit of device information ? capacity ? means bit no. 24 23 22 21 1m or 1.15m 0 0 0 1 2m or 2.3m 0 0 1 0 4m or 4.5m 0 0 1 1 8m or 9m 0 1 0 0 16m or 18m 0 1 0 1 32m or 36m 0 1 1 0 note42. bit of device information ? v dd ? means bit no. 27 26 25 3.3v 0 0 0 2.5v 0 0 1 1.8v 0 1 0 1.5v 0 1 1
mitsubishi lsis m5m5y5636tg ? 25,22,20 18874368-bit(524288-word by 36-bit) network sram 26 mitsubishi electric advanced information m5m5y5636tg rev.0.0 package outline 209(11x19) bump ball grid array(bga) pin pitch 1.0mm refer to jedec standard ms-028, variation bc, which can be seen at: http://www.jedec.org/download/search/m s-028c .pdf
mitsubishi lsis m5m5y5636tg ? 25,22,20 18874368-bit(524288-word by 36-bit) network sram 27 mitsubishi electric advanced information m5m5y5636tg rev.0.0 revision history ? jun/06/2001 rev.0.0 first revision

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